1. Field of the Invention
The present invention relates to an IC (Integrated Circuit) memory card for storing image data, character data or similar data and, more particularly, to an IC memory card system using an IC memory card incorporating an SRAM (Static Random Access Memory), EEPROM (Electrically Erasable Programmable Read Only Memory) or similar semiconductor memory. The present invention is also concerned with such an IC memory card and a data inputting and outputting system applicable to the IC memory card system.
2. Description of the Related Art
Today, it is a common practice with a digital electronic still camera or similar imaging apparatus to store image data representative of shots or pictures in an IC memory card incorporating a semiconductor memory. While an SRAM has been predominant as an IC memory for the above application, an EEPROM is also attracting attention due to, among others, the inherently low cost thereof. Preferably, therefore, a digital electronic still camera should be provided with an interface capable of accommodating both of a memory card with an SRAM and a memory card with an EEPROM, as needed.
An interface having the above-stated capability may be implemented as an interface connector having twenty pins, as proposed by Japan Electronic Industry Development Association (JEIDA) in "IC MEMORY GUIDELINE", 3rd Edition. According to this GUIDELINE, when the input and output of data from the IC memory card is implemented by an 8-bit parallel transfer bus, the interface connector is provided with eight data terminals. Then, not only data to be written to or read out of a memory chip but also an address designating the address location of the data in the memory card are applied to the eight data terminals. The address and the data are distinguished from each other by the logical states of two state terminals. When the address designating the address location of the memory chip is made up of a plurality of bytes, each byte is indicated by a particular combination of the logical states of the state terminals. For example, assuming an IC memory card using an SRAM whose capacity exceeds sixty-four kilobytes, the address is made up of three bytes. Then, the state terminals are indicative of the lower one of the three bytes to be read when both are in a low level, the middle one of the three bytes when one state terminal is in a low level and the other state terminal is in a high level, and the higher one of the three bytes when the former is in a high level and the latter is in a low level. Further, when both of the two state terminals are in a high level, they are indicative of reading or writing of data. The reading and the writing of data are distinguished from each other by the logical state of a read terminal and that of a write terminal provided independently of the state terminals. Specifically, data are read out when the read terminal goes high or data are written in when the write terminal goes high. The memory card writes or reads data in or out of the memory chip in response to control signals sent from an electronic still camera or similar host to such control terminals. When the read terminal is in a high level and both of the state terminals are in a low level, a status representative of the kind, capacity and so forth of the memory chip and a flag representing the instantaneous control condition of the card are read out of the card.
The conventional IC memory card with the above-described type of interface connector is provided with a control circuit for controlling the writing and reading of data out of the memory chip. When the memory card is removably loaded on a camera or similar host, the control circuit reads the status of the card to inform the host of the adaptability of the card and, on receiving an address made up of a plurality of bytes from the host, designates a corresponding address location of the memory chip. Subsequently, as the host sends a timing clock signal to a clock terminal also included in the connector, the control circuit sequentially increments the address to read data out of the memory chip or to write data therein.
However, the conventional IC memory card system has the following problem. Since the interface connector has only twenty pins as input/output terminals, an extra function cannot be added to the memory card unless one or more of the pins is exclusively allocated thereto. On the other hand, only four different states, including the writing of data, are available with the two state terminals of such a connector. Hence, when the address is made up of four or more bytes, i.e., when the storage capacity of the memory chip exceeds sixty-four kilobytes, an extra terminal for receiving a state signal is required. It follows that the conventional data inputting and outputting system is not practical when it is desired to add an extra function and increase the storage capacity.
In the light of the above, Japanese Patent Application No. 257380/1990 discloses an IC memory card capable of distinguishing all of the expected states with an address/data terminal distinguishing an address and data by a logical bilevel state (high or low), a read/write terminal distinguishing writing and reading by a bilevel state, and a bus clock terminal synchronous to an address or data on a byte basis, and capable of setting an address with no regard to the number of bytes. However, the problem with this type of memory card is that, when implemented by an EEPROM, it has to make a decision on the erasure of data and generate an erase signal within itself. The memory card, therefore, needs complicated control circuitry and cannot operate at high speed, compared to a memory card using an SRAM.
Moreover, assume that an error occurs while data are being sequentially written to the IC memory card having the above-mentioned three terminals or to any other conventional memory card. Then, the host cannot accurately locate the address of the memory card where the error has occurred, i.e., determine up to which address data have been written. The host, therefore, has to write the data all over again or has to start writing data again at or around the address in question on the basis of the content of a counter built therein and synchronous to a counter incorporated in the memory card. However, since the counter built in the host, or system, and the actual write address of the card often fail to coincide due to noise or similar cause, causing the system to count the address in synchronism with the card is not efficient. Particularly, when the storage capacity of the memory card and, therefore, the number of addresses is increased, the counter incorporated in the system would need to be scaled up and this would complicate the circuitry and increase the cost.